Master Thesis - SAR ADC comparator layout generator design in 28 nm TSMC technology
Your future responsibilities
- Literature (re)search regarding comparator designs.
- Literature (re)search regarding analog layout techniques.
- Coded comparator layout generator within BAG framework.
- Publication of the results at a conference or in a scientific journal.
- Experience in Cadence analog design flow (from schematic to post-layout simulation).
- Python knowledge.
- Linux knowledge is a plus.
- Team player, self motivated and goal oriented.
Important FactsThe starting date of this position is flexible.
This position is endowed with a gross monthly salary of € 1000,-/ for 15/h a week based on the collective agreement for research („Forschungs-Kollektivvertrag“).
The weekly hours are flexible and we are happy to discuss further options.
The contract is valid for 7 months.