Master Thesis - SAR ADC comparator layout generator design in 28 nm TSMC technology

RF Systems

Villach/Linz/Graz/

In this master thesis new design methodology will be used for SAR ADC comparator layout generator design in 28nm TSMC technology. The candidate will familiarize himself/herself with the design framework (based on BAG (Berkeley Analog Generator)) with Python as a scripting tool and Cadence as a generator execution tool (co-supervised). She/he will identify the needed blocks and propose comparator floorplan (supervised) and search through already available layout generators database. In addition the candidate will identify and analyze similar layout generators (self-learning) and adapt the most fitting layout generator scripts to fit proposed floorplan (execution). She/he will write his/her own script (from scratch) for missing blocks or interconnections towards successful competition of the comparator layout generator.

Your future responsibilities

  • Literature (re)search regarding comparator designs.
  • Literature (re)search regarding analog layout techniques.
  • Coded comparator layout generator within BAG framework.
  • Publication of the results at a conference or in a scientific journal.

Your profile

  • Experience in Cadence analog design flow (from schematic to post-layout simulation).
  • Python knowledge.
  • Linux knowledge is a plus.
  • Team player, self motivated and goal oriented.

Important Facts

The starting date of this position is flexible.
This position is endowed with a gross monthly salary of  € 1000,-/ for 15/h a week based on the collective agreement for research („Forschungs-Kollektivvertrag“).
The weekly hours are flexible and we are happy to discuss further options.
The contract is valid for 7 months.

Become part of Silicon Austria Labs

The top research center for electronic based systems (EBS). Unfold the future, unfold yourself.
Your browser is out of date!

Update your browser to view this website correctly. Update my browser now

×