Senior Scien­tist for RFIC Design for PLL/​Frequency Synthe­si­zers


Science Park 1, Alten­berger Straße 69, 4040 Linz, Austria

Silicon Austria Labs is perfor­ming cutting-edge re­search in its world-class mmWave RF Lab on the physical layer of RF systems for future 5G/​6G (UE, front and back-haul), and milli­meter-wave imaging/​sensing/​radar appli­ca­tions. In this domain, the mmWave RF Lab colla­bo­rates closely with the Johannes Kepler Univer­sity Linz and leading industry part­ners on e.g. RF/​milli­meter-wave trans­ceiver archi­tec­tures robust in terms of inter­fe­rence and coexis­tence, reconfigurable RF systems for trans­cei­vers and RF/​milli­meter-wave front-end modules (archi­tec­tural reuse and/​or resource sharing), and large-scale phased-array antennas and beam­for­ming struc­tures, which are targe­ting milli­meter-wave and sub-Tera­hertz commu­ni­ca­tions (5G, 6G), radars and imagers. In support of the design activi­ties the mmWave RF Lab is equipped with the best in-class test infra­struc­ture covering the GHz and low THz frequency range.

Your future responsibilities

  • System and circuit solu­tions for multi-gigabit wire­less chips
  • Frequency synthe­sizer/​PLL archi­tec­ture selec­tion
  • Imple­men­ting blocks and docu­men­ting design towards formal design reviews
  • Drive layout and top-level simu­la­tions to vali­date top-level inte­gra­tion
  • Take lab measu­re­ments to vali­date analog designs

Your profile

  • Solid expe­ri­ence in
    • PLL or clock/​frequency gene­ra­tion design 
    • Under­stan­ding of RF/​high-speed (10GHz+) issues 
    • Perfor­ming analog custom layout
    • Phase noise/​jitter, BW & power consump­tion design  trade-offs
  • High proficiency in system specification & ability to trans­late system into circuit requi­re­ments at IC level
  • Deep under­stan­ding of funda­men­tals, inclu­ding
    • Detailed tran­sistor level design 
    • Control/​feed­back loop stabi­lity analysis 
    • Device physics is a plus
  • Design expe­ri­ence in advanced CMOS nodes (FD-SOI, FinFET, bulk) is a plus
  • Insights into packa­ging effects, supply isola­tions, high frequency ESD struc­tures & circuit layout for optimum perfor­mance 
  • Expe­ri­ence in simu­la­tion and design of lumped & distri­buted passive struc­tures
  • Using EDA CAD tools (Cadence, Syno­psys, Mentor, Ansys, etc.) 
  • Proven expe­ri­ence in measu­ring IC perfor­mance and debug of design to corre­late simu­la­tions to measu­re­ments
  • Masters degree with 5+ years in related area of exper­tise or PhD with 2 years of expe­ri­ence

Important Facts

  • Begin­ning of the employ­ment: as soon as possible
  • This posi­tion is endowed with a gross annual salary of € 52,584 based on the collec­tive agree­ment for re­search („Forschungs-Kollek­tiv­ver­trag“) and depen­ding on your expe­ri­ence and skills.

Become part of Silicon Austria Labs

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